An N-bit barrel shifter, where N is the bit width of the barrel shifter, is a combinational logic circuit with N data input bits, N data output bits, and N control inputs which may be encoded in log.sub.2 N bits. The N data input bits are an input word. The N data output bits are the input word either rotated or shifted by the number of bit positions, designated a shift value, determined by the control inputs. A barrel shifter can be employed to shift either left or right and the shift value can take on any value in the range +(N-1) to -(N-1). Barrel shifters can accommodate only left shifts, only right shifts, or either left or right shifts. Rather than provide two barrel shifters, one for left shifts and another for right shifts, barrel shifters often include appropriate multiplexing to accommodate either left or right shifts. Such barrel shifters are known as bidirectional barrel shifters. Bidirectional barrel shifters permit greater flexibility in system design since the shift value and direction of shift are often not known in advance. Thus, both a shift value and a shift direction need to be provided to a bidirectional barrel shifter as control inputs. With two input quantities, there are four possible combinations: a positive right shift; a negative right shift (which is actually a left shift); a positive left shift; and a negative left shift (which is actually a right shift). A barrel shifter has a dominant shift direction and to shift in the other direction requires a conversion of the shift value to a value that is the difference between the bit width of the barrel shifter and the shift value. Barrel shifters make a data path a single stage and decode an m-bit shift value into 2.sup.m -1 control bits to control the barrel shifter.
Barrel shifters can be used to provide arithmetic or logic shifts, as well as a rotate operation. In a left shift, each bit of the input word is shifted to the left in the output word by the number of bit locations indicated by the shift value. The low order bits of the output word are zero filled. In a right shift, each bit of the input word is shifted to the right by the number of bit locations indicated by the shift value to produce the output word. The high order bits are filled with sign extensions for arithmetic shifts or zeros for logic shifts. A rotate operation can occur in either the left or right directions. A rotate operation provides that each bit shifted out of one end of a word reappears and is shifted into the other end of the word.
Computations in digital signal processors are performed with two's complement hardware. The shift value must be represented in a two's complement number system, which is the radix complement for binary numbers. Two's complement representations of numbers can be obtained from a binary representation by complementing the individual digits, and adding one. In the two's complement number system, the most significant bit is one for negative numbers and zero for positive numbers. Zero is considered positive because its sign is positive. For an m-bit representation, numbers may range from -(2.sup.m-1) through through +(2.sup.m-1 -1) with one negative number, -2.sup.m-1, that does not have a positive counterpart.
A two's complement representation of a number can be produced from a binary representation using exclusive OR gates (EOR) and an adder as shown in the schematic diagram of FIG. 3 illustrating a prior art technique for controlling a barrel shifter. The shift direction is represented as a 0 for a right shift and a 1 for a left shift. The shift direction 302 is combined with the sign bit 304 of the shift value 308 in exclusive OR gate 300 to produce a modified shift direction 306. The sign bit is 0 for positive shift values and 1 for negative shift values. The bits of the shift value 308 are exclusive ORed with the shift direction 302 in EOR gates 310.sub.0 through 310.sub.m-1 and 311 to produce a ones' complement of the bits at the output 312. To accommodate the shift direction, either a zero for shifts in the dominant direction of the barrel shifter, or the bit width of the barrel shifter, is selected by multiplexer 316 as controlled by select input 306, to be added to the two's complement representation of the shift value in full adder 318. The shift direction 302 is added to the ones' complement representation and either zero or the bit width of barrel shifter 314, as selected by multiplexer 316, in full adder 318 to produce a two's complement representation of the shift value at output 320. The most significant bit of output 320 is discarded. The output from full adder 318 is always positive. The low order m bits of output 320 of full adder 318 is an encoded shift value, represented by m bits that are decoded in decoder 324 to provide N control signals 326 used to control barrel shifter 314. Barrel shifter 314 also receives the modified shift direction 306 directly and, in response to the control inputs 326, produces as its output 330 a shifted version of the input word 328.
This prior art technique has the shortcoming of introducing a delay in producing the N control signals used to control barrel shifter 314. The delay results from operation of adder 318. A delay in producing the control inputs to barrel shifter inherently introduces a delay in operation of the barrel shifter.